IMPLEMENTATION AND COMPARISON OF 64-BIT MULTIPLIERS OF UNSIGNED NUMBER THROUGH REDUCTION SCHEME

Authors

  • Ayesha Nasir
  • Usama Anwar
  • Muhammad Aqeel Aslam

Keywords:

FPGA, Logic Cells, Multiplier, Reduction Methods

Abstract

Multiplication algorithms good multiplication algorithms are critical towards improving the overall performance of computer systems because multiplication is one of the basic procedures in digital computing. This study presents our analysis and comparison of three 64-bit multiplication algorithm Booth multiplier, Montgomery multiplier using Carry Look-Ahead (CLA) adders and Wallace Tree multiplier using both full and half adders. The analysis investigates the execution time, parameter of area utilization of both multiplier systems and exhaustively evaluates their pros and cons in practice. In our results, Wallace Tree Multiplier is a better option because of its speed and area utilization hence it is preferable to use in the high-performance computing systems where minimal time was saved in its completion. This study offers much information regarding the best selection of multiplication approach to apply to a particular scenario, which forms the foundation of enhancing mathematical functions in the digital world

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Published

2026-03-16

How to Cite

Ayesha Nasir, Usama Anwar, & Muhammad Aqeel Aslam. (2026). IMPLEMENTATION AND COMPARISON OF 64-BIT MULTIPLIERS OF UNSIGNED NUMBER THROUGH REDUCTION SCHEME. Spectrum of Engineering Sciences, 4(3), 2411–2423. Retrieved from https://www.thesesjournal.com/index.php/1/article/view/3305