MATHEMATICAL OPTIMIZATION OF ANALOG COMPUTE-IN-MEMORY: TRADE-OFFS BETWEEN LINEARITY, NOISE, AND NON-LINEAR ACTIVATION IN MEMRISTOR CROSSBARS

Abstract

The von Neumann bottleneck in deep neural network inference can be addressed by analog compute-in-memory (CiM) by analog matrix-vector multiplication performed in the memory array. This can, in principle, reduce energy consumption by one to two orders of magnitude in comparison to digital accelerators. However, in practice, the accuracy of inferences is far from perfect due to analog non-idealities such as device noise, conductance programming variability, ADC quantization, and signal saturation, making analog CiM impractical for real-world applications. This paper proposes a comprehensive mathematical optimization framework by combining the device physics, circuit design, and neural network training to obtain the minimum inference error for analog CiM systems. A closed-form statistical model of error propagation through memristor crossbar is first developed, accounting for thermal noise, shot noise, programming noise, and quantization of the ADC.Thermal noise, shot noise, programming noise and ADC quantization are first captured in a closed-form statistical model of error propagation through a memristor crossbar. Based on this model, we formulate the optimization of the conductance range [G_min, G_max ] and the full-scale (FS) of the ADC as a convex program and obtain globally optimal parameters that provide a balance between signal strength, noise, and risk of signal saturation. We then present a noise-aware version of the digital ReLU, f ̃_"ReLU" _ ( x ̃ ) to incorporate the distribution of analog noise and the ADC saturation during fine-tuning so that the network can learn hardware-robust representations. Our framework is validated on a simulated 128x128 memristor crossbar, with the MNIST database and a 3-layer multi-layer perceptron. Compared with naive analog mapping with the accuracy loss of 6.74% against an ideal digital baseline, our approach retrieves 86.8% of this loss in the test, resulting in 97.32% accuracy (within 0.89% of digital), and retains the energy efficiency of analog computing. The optimized system decreases output mean squared error by 86% compared to naive analog mapping (14× compared to digital), and increases energy efficiency by 11% compared to naive analog mapping (14× compared to digital). Ablation studies indicate that both convex optimization and noise-aware activation are important for recovery of accuracy, and sensitivity analysis proves that the framework allows for a viable 3-bit ADC operation (93.8% accuracy).  The results show that algorithm-hardware co-design, based on convex optimization and noise-aware learning, can bridge this accuracy gap between analog and digital computing, while maintaining the energy advantage of in-memory architectures. The architecture is independent – which could adapt to any resistive memory technology – compute-efficient – with the microseconds per layer – and easily deployable to practical edge analog AI accelerators.

Keywords : Compute-in-memory · Memristor crossbar · Analog neural networks · Convex optimization · Noise-aware activation · Hardware-software co-design · Edge AI.