A COMPREHENSIVE REVIEW OF DESIGN AND EVALUATION OF EMERGING TRANSISTOR TECHNOLOGIES FOR ADVANCED CMOS SCALING

Abstract

But with the decreasing size of an integrated circuit, the conventional structure of a transistor cannot satisfy the requirements of the present era in terms of efficiency and power consumption. While conventional planar MOSFETs and subsequently FinFETs have served the semiconductor industry quite effectively till date, any further reduction in size of the transistor has faced severe limitations such as increased leakage currents and electrostatic breakdown. Technologies such as gate-all-around field-effect transistors, vertically stacked nanosheets, nanowire-based devices, and complementary FETs offer improved gate control and better scalability for advanced technology nodes. This review discusses recent research, published between 2020 and 2025, on how these emerging devices stack up against conventional CMOS structures. Architectural changes, fabrication concerns, performance trade-offs, and long-term feasibility are discussed in this paper with the aim of comprehending how CMOS technology will be able to evolve beyond the FinFET era.